Strategies for Heterogeneous Multi-Core Processing Based on Graph Programming

J. Fryer, Paulo Garcia
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Abstract

In this paper, we explore strategies for automated parallelization and reconfiguration across heterogeneous multi-core processor, based on a programming paradigm and an associated model of computation designed for efficient and automated parallelization across processing elements, efficient reconfiguration (i.e., mapping of computational tasks across processing elements), and combining synchronous and asynchronous I/O handling within the same conceptual programming model. We introduce an analytical model of parallelization, unlocked by graph programming, that can effectively reason about power and performance tradeoffs in heterogeneous multi-core, and inform reconfiguration strategies. We analyze the implications of our model through an analysis of reconfiguration scenarios given a program’s characteristics; our analysis quantifies the benefits of reconfiguring software for higher levels of parallelism, given an amount of data left to process. We empirically validate the performance advantage of our automatic parallelism capabilities through Horde, an open source graph programming interpreter; in our experiments, automatic parallelization from one to four cores improves average case execution time by a factor of 2 and worst case execution time by a factor of 3. When reconfiguring across heterogeneous processors, our model can predict execution time with an average error of 9.45%.
基于图编程的异构多核处理策略
在本文中,我们探索了跨异构多核处理器的自动并行化和重新配置策略,该策略基于一种编程范式和一种相关的计算模型,该模型旨在跨处理元素进行高效和自动化的并行化,有效的重新配置(即跨处理元素的计算任务映射),并在同一概念编程模型中结合同步和异步I/O处理。我们引入了一个并行化的分析模型,通过图形编程解锁,可以有效地推断异构多核中的功率和性能权衡,并告知重新配置策略。我们通过分析给定程序特征的重新配置场景来分析我们的模型的含义;我们的分析量化了重新配置软件以获得更高级别并行性的好处,并给出了需要处理的数据量。我们通过Horde(一个开源的图形编程解释器)经验验证了自动并行能力的性能优势;在我们的实验中,从1核到4核的自动并行化将平均情况执行时间提高了2倍,将最坏情况执行时间提高了3倍。当跨异构处理器重新配置时,我们的模型可以预测执行时间,平均误差为9.45%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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