Towards a New Quasigroup Block Cipher for a Single-Chip FPGA Implementation

Abstract

In earlier work the authors reported on methods they investigated to implement quasigroup block encryption in hardware, with an emphasis on low cost. The aim was to design and deliver a hardware design solution that was inexpensive but did not sacrifice encryption security; the desired target for the design is low-bandwidth, low-cost areas such as Supervisory Control And Data Acquisition (SCADA) systems. Here the authors report on further refinements of this design with the aim of making a single-chip solution.