Design of low power SRAM on Artix-7 FPGA

Abstract

SRAM is associated with cache memory inside computer system, it increases overall speed of the system. In this work 64kb SRAM is synthesized and simulated on Artix-7 FPGA board by using different Input-Output Standard techniques. For designing SRAM, HSTL_I, HSTL_I_18, HSTL_II and HSTL_II_18 IO Standards are used and power dissipation is calculated on various range of operating frequencies and find HSTL_I is most power efficient IO Standard among these other IO Standards. at 1GHz, 2GHz and 3GHz operating frequency if HSTL_I is used in place of HSTL_II_18, 26.38%, 17.18% and 11.12% power can be saved.