A QPLL-timed direct-RF sampling band-pass ΣΔ ADC with a 1.2 GHz tuning range in 0.13 µm CMOS

Abstract

A direct-RF sampled band-pass ΣΔ modulator enables reconfigurable RF A/D conversion. It features a programmable narrow-band Q-enhanced low-noise amplifier and a phase-locked loop implemented using a low-phase-noise injection-locked harmonic-filtering quadrature voltage-controlled oscillator. The quadrature outputs of the PLL provide phase synchronization between a raised-cosine DAC and the quantizer. The three-tap raised-cosine finite-impulse response filter is embedded in the RF DAC. A complete sampling receiver demonstrates progress towards Software-Defined Radio (SDR) applications. Implemented in 0.13 µm CMOS, it consumes 41 mW and achieves maximum SNDR values of 50 dB, 46 dB and 40 dB over a 1 MHz bandwidth with 796.5 MHz, 1.001 GHz and 1.924 GHz input carrier frequencies. The measured PLL phase noise is −113 dBc/Hz at an offset frequency of 1 MHz with a −74.5 dBc carrier-reference spur; the RMS period jitter is 1.38 ps at 3.2 GHz.