Flow machine diagrams for VHDL code

Abstract

This paper discusses the process of generating abstract graphical models from VHDL. This process can be utilized to enhance the maintenance and comprehensibility of legacy textual code by transforming it into more readable and comprehensive models. The paper proposes use of a different diagrammatic language in this field, an alternative to UML. The proposed language is applied to describe the AND gate and half-adder and also to model a vending machine. The resultant high-level descriptions provide a viable tool for understanding VHDL code written by someone else and for documenting, communicating among team members, and teaching of VHDL.