Non-ideality Analysis of Current steering DAC

Abstract

Some non-ideal factors during circuit design of current steering digital to analog converter (DAC) are analyzed and summarized in this paper. A 12-bit classic current steering DAC has been analyzed and effects of these non-ideal factors has been validated. Meanwhile, non-idealities are also double checked in post-layout simulation. The whole circuit has been taped out in TSMC 0.25um BCD process, test and simulation results are compared at last. The comparison results show that the non-ideal analysis can be used to estimate non-linearity of current steering DAC and guide the circuit design of DACs.