Modeling the effect of chip failures on cache memory systems

Abstract

Two statistical models are developed to estimate the effect of chip failures on cache memory systems. The first one predicts the degradation in the expected Read time taking into account the different failure modes of a memory chip. It is seen that there is a significant degradation in the expected access time after only four weeks of operation even if failed words are deallocated. The second model estimates the degradation in the Miss ratio due to the deallocation of failed sections of cache. Both models can help in setting suitable preventive maintenance schedules as well as in making design decisions.