Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture

Atin Mukherjee, A. Dhar
{"title":"Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture","authors":"Atin Mukherjee, A. Dhar","doi":"10.1109/ISED.2012.21","DOIUrl":null,"url":null,"abstract":"Fault Tolerance is the ability of a system to detect and recover from a fault in the system. By incorporating fault tolerant features in any architecture, reliability and durability of the system increases at the cost of increased hardware. There must be a good tradeoff between cost and system performance. For all critical applications the system must reconfigure itself automatically to continue its normal operation even if any fault occurs. Again adder is the most essential block in any digital architecture. In this article we will design a four bit fault tolerant ripple carry adder and also discuss how design costs and number of faults to be tolerated are affected with the size of sub-module chosen to make the system self-reconfigurable.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Symposium on Electronic System Design (ISED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISED.2012.21","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9

Abstract

Fault Tolerance is the ability of a system to detect and recover from a fault in the system. By incorporating fault tolerant features in any architecture, reliability and durability of the system increases at the cost of increased hardware. There must be a good tradeoff between cost and system performance. For all critical applications the system must reconfigure itself automatically to continue its normal operation even if any fault occurs. Again adder is the most essential block in any digital architecture. In this article we will design a four bit fault tolerant ripple carry adder and also discuss how design costs and number of faults to be tolerated are affected with the size of sub-module chosen to make the system self-reconfigurable.
一种用于容错VLSI架构的自重构加法器设计
容错是系统检测系统故障并从故障中恢复的能力。通过在任何体系结构中加入容错功能,系统的可靠性和耐用性都会提高,但代价是增加硬件。在成本和系统性能之间必须有一个很好的权衡。对于所有关键应用程序,系统必须自动重新配置自己,以便即使发生任何故障也能继续正常运行。加法器是任何数字架构中最重要的模块。在本文中,我们将设计一个4位容错纹波进位加法器,并讨论为使系统自重构而选择的子模块大小对设计成本和容错数量的影响。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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