Design considerations on CMOS limiting amplifiers for wearable biomedical systems

Abstract

This paper presents design considerations on CMOS limiting amplifiers to be used as basic building blocks for power-efficient logarithmic amplifiers. The impact of mismatches and device-level properties on sensitivity and gain-bandwidth product is discussed. To this end, a comparison of several types of low-voltage gain cell topologies is presented. Based on statistical (Monte Carlo) results, a high-sensitivity eight-stage limiting amplifier tolerant of process and mismatch variations was designed in 0.35-µm CMOS technology to operate over a dc-to-20-MHz bandwidth. The proposed limiting amplifier draws 280 µA from a 2-V supply and achieves a voltage gain of 75 dB.