Obstacle-Aware Group-Based Length-Matching Routing for Pre-Assignment Area-I/O Flip-Chip Designs

Abstract

A robust redistribution layer (RDL) router is required for advanced package designs, where the length-matching constraint for a group of nets needs to be considered to preserve good timing properties at the package level. For area-I/O flip-chip design with pre-assigned nets on RDLs, we propose the first group-based length-matching routing framework that can simultaneously minimize the wirelengths of an arbitrary group of nets with and without equal-length constraints, based on an equal-length-aware A*-search algorithm and a bounded sliceline grid (BSG) snaking one. For the irregular structure of the area-I/O flip-chip design, we apply Delaunay triangulation and Voronoi diagram to model the routing resources more precisely. To effectively consider the equal-length constraints in the earlier stage, we first profile the routing resource to obtain an approximation of the longest net, and then adopt the equal-length-aware A*-search algorithm to extend shorter nets to match the estimated longest net. A BSG-based snaking method is then applied to meet the equal-length constraint, while preserving the minimized wirelength of unconstrained nets. Experimental results demonstrate that our framework can solve all benchmarks effectively and efficiently.