Relative scheduling under timing constraints

Abstract

Scheduling techniques are used in high-level synthesis of integrated circuits. Traditional scheduling techniques assume fixed execution delays for the operations. For the synthesis of ASIC designs that interface with external signals and events, operations with unbounded delays. i.e., delays unknown at compile time, must also be considered. A relative scheduling technique that supports operations with fixed and unbounded delays is presented. The technique satisfies the timing constraints imposed by the user, which places bounds between the activation of operations. A novel property called well-posedness of timing constraints is analyzed that is used to identify consistency of constraints in the presence of unbounded delay operations, and an approach to relative scheduling is presented that yields a minimum schedule that satisfies the constraints, or detects if no schedule exists, in polynomial time.<>