Tutorial I: Influence of IC packaging technology on ESD robustness of components

Abstract

The IC packaging technology has a surprisingly large influence on an IC's electrostatic discharge (ESD) robustness at both the component and system levels. For charge device model (CDM) component-level ESD, the package determines the amount of energy dissipated in the die, and for both system and component-level ESD, the package determines the current return path. This tutorial will explore those phenomena and demonstrate how the on-chip ESD protection network design should be mindful of the package design. The effect of 3D integration will also be addressed.