{"title":"Memory-based implementation of a Petri net and its application to a programmable controller","authors":"N. Chang, Jaehyun Park, Kyeonghoon Koo, W. Kwon","doi":"10.1109/IECON.1993.339007","DOIUrl":null,"url":null,"abstract":"In this paper, a memory-based Petri net implementation is discussed. To realize a memory-based implementation, a sub-class Petri net model is suggested. The suggested model, B-Petri net, is a marked graph whose numbers of input places and output places of a transition are limited to two. The B-Petri net has the same modeling power as a marked graph. The complexity of the B-Petri net is analyzed, and the hardware implementation architecture of a programmable controller based on it is also suggested. The memory tables have realizable memory size, and they are reduced well in case of some real applications like a programmable controller.<<ETX>>","PeriodicalId":132101,"journal":{"name":"Proceedings of IECON '93 - 19th Annual Conference of IEEE Industrial Electronics","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IECON '93 - 19th Annual Conference of IEEE Industrial Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IECON.1993.339007","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this paper, a memory-based Petri net implementation is discussed. To realize a memory-based implementation, a sub-class Petri net model is suggested. The suggested model, B-Petri net, is a marked graph whose numbers of input places and output places of a transition are limited to two. The B-Petri net has the same modeling power as a marked graph. The complexity of the B-Petri net is analyzed, and the hardware implementation architecture of a programmable controller based on it is also suggested. The memory tables have realizable memory size, and they are reduced well in case of some real applications like a programmable controller.<>