Understanding the Architectural Characteristics of EDA Algorithms

Abstract

Currently, the release of different chip products has come to a burst. Time-to-market period of these products has been shortened to an extreme, nearly 8 to 12 months. To reduce production period, hardware architects try to shorten every design and manufacture stage. Therefore, it has become one of the major concerns for them that how to accelerate electronic design automation (EDA) tools, which have been widely used throughout the lifetime of chip design and manufacture. While many prior efforts have done in-depth works on different acceleration techniques, such as IC-based, FPGA-based, or GPUbased, to our best knowledge, there has been no systematic study towards the architectural characteristics analysis for these EDA algorithms. This may impede the further optimizations and acceleration for them. In this paper, we make the first attempt to construct an EDA benchmark suite (EDAbench for short) for architectural design, parallel acceleration, and system optimization. EDAbench covers representative modern EDA algorithms. We then evaluate predominant architectural characteristics from three aspects including computation characteristics, memory hierarchy, and systematic characteristics. Experimental results reveal that there are some vital gaps between existing hardware and the requirements of EDA algorithms. Based on the analysis, we also give out some insights and propose suggestions for future optimization, acceleration, and architecture design.