Improved modulo-(2n ± 3) multipliers

Abstract

Modular adders and multipliers have applications in residue number system (RNS) arithmetic, cryptography, and error-checking, where general architectures are usually designed for moduli of the form 2n±k ± 1, with very efficient realizations. However, less efficient arithmetic circuits also occasionally appear in the relevant literature for moduli of the form 2n ± δ, where δ is an odd integer and δ ≠1. In particular, adders, multipliers and RNS converters have been recently offered for modulo-(2n ± 3). In this paper, we address a recent work on modulo-(2n ± 3) multipliers that are realized as normal n-bit multipliers, followed by conversion of 2n-bit products to RNS residues. We aim to enhance the performance of such modular multipliers via eliminating the carry propagate adder that operates at the end of preliminary binary multiplication. Analytical and synthesis based evaluation has shown improvements in latency and power dissipation. Also our designs require less area consumption for the same delay.