Reducing power consumption for system on programmable chip by scheduling tasks

Abstract

Reducing power consumption has become a main objective in the System on Programmable Chip design. Indeed, increasing integration rates and clock frequencies, it becomes necessary to design techniques to reduce power consumption. These techniques are interesting to satisfy the criteria of autonomy, reliability and cost for embedded systems. In this context, we propose an algorithm to schedule tasks obtained from a hardware/software partitioning and running in parallel. In fact, we reduce their operating frequency tasks in an affordable limit to decrease dynamic power consumption without increasing the overall time execution of the application.