A 1mW CMOS limiting amplifier and RSSI for ZigBee™ applications

Abstract

This paper presents a low-power intermediate frequency (IF) limiting amplifier (LA) and received signal strength indicator (RSSI). The LA and RSSI are designed for ZigBee™ receiver at 2MHz IF. To save power, two local loops for offset correction are used in LA chain and a sensitivity of -56dBm is achieved. Each LA gain stage employs cascade diodes load to avoid driving the diode load into velocity saturation region. The indication rang is 50dB within ±2dB linearity error. The core area is 0.11×0.31mm2 using a SMIC 0.18-μm CMOS technology. The overall power consumption is 1mW from a 1.8V supply voltage.