Load-balanced Three-stage Switch Architecture

Abstract

A load-balanced two-stage switch is scalable and can provide close to 100% throughput. Its major problem is that packets can be mis-sequenced when they arrive at output ports. In a recent work, the packet mis-sequencing problem is elegantly solved by a feedback-based two-stage switch architecture. In this paper, we extend the feedback-based switch architecture from two-stage to three-stage to further cut down packet delay. The idea is to map the heavy flows to experience less middle-stage port delay using the switch fabric in the third stage. We show that the resulting three-stage architecture also ensures in-order packet delivery and close to 100% throughput. To identify heavy flows, a simple and practical traffic matrix estimation algorithm is also proposed. As compared with the original feedback-based two-stage switch architecture, the three-stage switch can cut down the delay performance by as large as 43.4% for a 32times32 switch under a hot-spot traffic pattern with input load at p=0.95. For random uniform traffic, the saving in delay is about 8%.