A Novel Low Power Dynamic Memory Architecture Using Single Supply 3T Gain Cell

Abstract

Design of memory consists of two different approaches namely, static random access memory (SRAM) and dynamic random access memory (DRAM). Traditionally SRAM has been used to design memory. The major problem to design a memory using SRAM is area, power and delay. The memories designed with SRAM will result in high power, high delay and consumes more area. To overcome this problem, a DRAM cell is designed witch results in low power, low area and low delay. There are certain disadvantages with these two designs, and to overcome limitations a new gain cell is designed in this paper. A 2Kb dynamic memory architecture has been designed using the proposed modified 3T gain cell. An architecture is designed with features of high speed, low power, and low delay. The dyanmic memory architecture is implemented using Cadence Analog Design Environment. The proposed and conventional dynamic memory architectures were compared in terms of power and delay for variable supply voltages and temperatures.