In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms

Young-kyu Choi, J. Cong, Zhenman Fang, Y. Hao, Glenn D. Reinman, Peng Wei
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引用次数: 27

Abstract

Conventional homogeneous multicore processors are not able to provide the continued performance and energy improvement that we have expected from past endeavors. Heterogeneous architectures that feature specialized hardware accelerators are widely considered a promising paradigm for resolving this issue. Among different heterogeneous devices, FPGAs that can be reconfigured to accelerate a broad class of applications with orders-of-magnitude performance/watt gains, are attracting increased attention from both academia and industry. As a consequence, a variety of CPU-FPGA acceleration platforms with diversified microarchitectural features have been supplied by industry vendors. Such diversity, however, poses a serious challenge to application developers in selecting the appropriate platform for a specific application or application domain. This article aims to address this challenge by determining which microarchitectural characteristics affect performance, and in what ways. Specifically, we conduct a quantitative comparison and an in-depth analysis on five state-of-the-art CPU-FPGA acceleration platforms: (1) the Alpha Data board and (2) the Amazon F1 instance that represent the traditional PCIe-based platform with private device memory; (3) the IBM CAPI that represents the PCIe-based system with coherent shared memory; (4) the first generation of the Intel Xeon+FPGA Accelerator Platform that represents the QPI-based system with coherent shared memory; and (5) the second generation of the Intel Xeon+FPGA Accelerator Platform that represents a hybrid PCIe-based (non-coherent) and QPI-based (coherent) system with shared memory. Based on the analysis of their CPU-FPGA communication latency and bandwidth characteristics, we provide a series of insights for both application developers and platform designers. Furthermore, we conduct two case studies to demonstrate how these insights can be leveraged to optimize accelerator designs. The microbenchmarks used for evaluation have been released for public use.
现代异构CPU-FPGA平台的微架构深入分析
传统的同构多核处理器无法提供我们从过去的努力中所期望的持续性能和能源改进。具有专用硬件加速器的异构体系结构被广泛认为是解决此问题的一个很有前途的范例。在不同的异构器件中,fpga可以重新配置以加速具有数量级性能/瓦特增益的广泛应用,正在吸引学术界和工业界越来越多的关注。因此,行业供应商提供了各种具有不同微架构特征的CPU-FPGA加速平台。然而,这种多样性给应用程序开发人员在为特定应用程序或应用程序领域选择适当的平台时带来了严峻的挑战。本文旨在通过确定哪些微体系结构特征会以何种方式影响性能来解决这一挑战。具体来说,我们对五个最先进的CPU-FPGA加速平台进行了定量比较和深入分析:(1)Alpha Data板和(2)Amazon F1实例,它们代表了传统的基于pcie的平台,具有私有设备内存;(3) IBM CAPI,代表基于pcie的系统,具有一致的共享内存;(4)第一代Intel Xeon+FPGA加速器平台,代表了基于qpi的系统与相干共享内存;(5)第二代Intel Xeon+FPGA加速器平台,该平台代表了基于pcie(非相干)和基于qpi(相干)的混合系统,具有共享内存。基于对它们的CPU-FPGA通信延迟和带宽特性的分析,我们为应用开发者和平台设计者提供了一系列见解。此外,我们进行了两个案例研究,以演示如何利用这些见解来优化加速器设计。用于评估的微基准已经发布供公众使用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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