{"title":"Advanced Encryption Standard Implemented on FPGA","authors":"Sujatha Hiremath, M. Suma","doi":"10.1109/ICCEE.2009.231","DOIUrl":null,"url":null,"abstract":"Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), and categorized as Computer Security Standard. The AES algorithm is a block cipher that can encrypt and decrypt digital information. The AES algorithm is capable of using cryptographic keys of 128, 192, and 256 bits. The Rijndael cipher has been selected as the official Advanced Encryption Standard (AES) and it is well suited for hardware. This paper talks of AES 128 bit block and 128 bit cipher key and is implemented on Spartan 3 FPGA. Synthesis results in the use of 2509 slices, 712 Flip flops, and 4762- 4 input Look Up Tables. The design target is optimization of speed and cost.","PeriodicalId":343870,"journal":{"name":"2009 Second International Conference on Computer and Electrical Engineering","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Second International Conference on Computer and Electrical Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCEE.2009.231","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16
Abstract
Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), and categorized as Computer Security Standard. The AES algorithm is a block cipher that can encrypt and decrypt digital information. The AES algorithm is capable of using cryptographic keys of 128, 192, and 256 bits. The Rijndael cipher has been selected as the official Advanced Encryption Standard (AES) and it is well suited for hardware. This paper talks of AES 128 bit block and 128 bit cipher key and is implemented on Spartan 3 FPGA. Synthesis results in the use of 2509 slices, 712 Flip flops, and 4762- 4 input Look Up Tables. The design target is optimization of speed and cost.