Level-3 BLAS on the TI C6678 Multi-core DSP

2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing Pub Date : 2012-10-24 DOI:10.1109/SBAC-PAD.2012.26

Murtaza Ali, E. Stotzer, Francisco D. Igual, R. V. D. Geijn

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引用次数: 32

Abstract

Digital Signal Processors (DSP) are commonly employed in embedded systems. The increase of processing needs in cellular base-stations, radio controllers and industrial/medical imaging systems, has led to the development of multi-core DSPs as well as inclusion of floating point operations while maintaining low power dissipation. The eight-core DSP from Texas Instruments, codenamed TMS320C6678, provides a peak performance of 128 GFLOPS (single precision) and an effective 32 GFLOPS(double precision) for only 10 watts. In this paper, we present the first complete implementation and report performance of the Level-3 Basic Linear Algebra Subprograms(BLAS) routines for this DSP. These routines are first optimized for single core and then parallelized over the different cores using OpenMP constructs. The results show that we can achieve about 8 single precision GFLOPS/watt and 2.2double precision GFLOPS/watt for General Matrix-Matrix multiplication (GEMM). The performance of the rest of theLevel-3 BLAS routines is within 90% of the corresponding GEMM routines.

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TI C6678多核DSP上的3级BLAS

数字信号处理器(DSP)通常用于嵌入式系统。蜂窝基站、无线电控制器和工业/医疗成像系统中处理需求的增加导致了多核dsp的发展以及在保持低功耗的同时包含浮点运算。来自德州仪器的八核DSP，代号为TMS320C6678，提供128 GFLOPS(单精度)的峰值性能和有效的32 GFLOPS(双精度)，仅为10瓦。在本文中，我们提出了该DSP的第一个完整的三级基本线性代数子程序(BLAS)例程的实现和性能报告。这些例程首先针对单核进行优化，然后使用OpenMP结构在不同的核上并行化。结果表明，通用矩阵-矩阵乘法(GEMM)的单精度GFLOPS/瓦特约为8，双精度GFLOPS/瓦特约为2.2。其余3级BLAS例程的性能在相应的GEMM例程的90%以内。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing

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