Design and analysis of 8T SRAM with assist schemes (UDVS) in 45nm CMOS

Abstract

In modern ICs designing, the process of integrating more on-chip memories on a chip leads SRAMs to reason for a huge amount of total power and area of a chip. Therefore, memory designing with dynamic voltage scaling (DVS) capability is necessary. However, optimizing circuit operation over a wide range of voltage is not easy due to trade-offs of transistor characteristics in low-voltage and high-voltage. Ultra Dynamic Voltage Scaling (UDVS) techniques are used in low voltage levels to minimize the power consumption. Designing memories with DVS capability is gaining more importance since active as well as leakage power can be reduced by voltage scaling. UDVS is to scale the supply voltage by using assists circuits for different modes of the cell operation. In this paper three write assist circuits for reduction in power and 8T cell circuits have been designed. First one is Capacitive W-AC approach to reduce the level of cell supply voltage. Second scheme is Transient Negative Bit-line Voltage write assist scheme for write operation without using any on-chip or off-chip voltage sources and third one is transient negative bit line scheme in which write operation is performed by increasing the strength of SRAM pass transistor. Read operation for reading the data from the cell without altering (destructive read operation) the cell data with low power consumption. In this paper at last 8T SRAM cell in 45nm technology is implemented with operating voltage 1V.