S. Yamamoto, T. Yokoyama, T. Kunihisa, M. Nishijima, M. Nishitsuji, K. Nishii, O. Ishikawa
{"title":"High efficiency GaAs power MMIC operating with a single 3.0 V supply for PACS handsets","authors":"S. Yamamoto, T. Yokoyama, T. Kunihisa, M. Nishijima, M. Nishitsuji, K. Nishii, O. Ishikawa","doi":"10.1109/MTTTWA.1997.595106","DOIUrl":null,"url":null,"abstract":"A high efficiency 3-stage power MMIC operating with a single 3.0 V supply has been developed for 1.9 GHz PACS (low tier PCS) handsets. The pseudomorphic double heterojunction modulation doped FET (MODFET) has enabled a single 3.0 V operation. The MMIC includes all matching circuits (input, output and internal matching circuits), but drain and gate bias circuits are excluded from the MMIC chip to make the chip size small. The new MMIC realizes a high power added efficiency of 30.2% at output power of 24.5 dBm and 1.88 GHz with low adjacent channel leakage power of -60.0 dBc under a single 3.0 V bias supply condition. Total gain and operating current are 32.3 dB and 307 mA, respectively.","PeriodicalId":264044,"journal":{"name":"1997 IEEE MTT-S Symposium on Technologies for Wireless Applications Digest","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 IEEE MTT-S Symposium on Technologies for Wireless Applications Digest","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTTTWA.1997.595106","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A high efficiency 3-stage power MMIC operating with a single 3.0 V supply has been developed for 1.9 GHz PACS (low tier PCS) handsets. The pseudomorphic double heterojunction modulation doped FET (MODFET) has enabled a single 3.0 V operation. The MMIC includes all matching circuits (input, output and internal matching circuits), but drain and gate bias circuits are excluded from the MMIC chip to make the chip size small. The new MMIC realizes a high power added efficiency of 30.2% at output power of 24.5 dBm and 1.88 GHz with low adjacent channel leakage power of -60.0 dBc under a single 3.0 V bias supply condition. Total gain and operating current are 32.3 dB and 307 mA, respectively.