Investigation of Si_3N_4 Capping Layer and Embedded SiGe Effect on 90 nm CMOS Devices

Abstract

This paper highlights the effect of Si3N4 capping layer, embedded SiGe in the source/drain and SiGe layer on the bottom of the strained silicon for strained-silicon technology effect on 90 nm Complementary Metal Oxide Semiconductor (CMOS) performance focusing on threshold voltage and drain current parameters. Strained silicon is used to increase saturated NMOS and PMOS drive currents and enhance electron mobility. Compressive strain is introduced by two techniques strained in the PMOS channel using SiGe such as uniaxial strained and biaxial strained. Tensile strain is introduced in the NMOS channels by using a post siliconnitride capping layer. ATHENA and ATLAS simulators were used to simulate the fabrication process and to characterize the electrical properties respectively. It can be concluded that NMOS strained technology having high tensile stress improve by 46.9% drain current. PMOS strained technology having compressive stress using biaxial strained PMOS improve 16.4% while uniaxial strained PMOS improve 21.4%. The strained technology were the best on 90 nm for CMOS device is combination of Si3N4 film tensile strain for NMOS and uniaxial compressive strain for PMOS.