{"title":"A 4K×2K@60fps multi-standard TV SoC processor with integrated HDMI/MHL receiver","authors":"Chi-Cheng Ju, Tsu-Ming Liu, Huaide Wang, Yung-Chang Chang, Chih-Ming Wang, Chang-Lin Hsieh, Brian Liu, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Min-Hao Chiu, Sheng-Jen Wang, P. Chao, Meng-Jye Hu, Ryan Yeh, Ted Chuang, Hsiu-Yi Lin, Chung-Hung Tsai","doi":"10.1109/VLSIC.2014.6858389","DOIUrl":null,"url":null,"abstract":"A first-reported 4K×2K@60fps digital TV SoC processor supporting 9 video formats and integrating HDMI/MHL receiver is fabricated in a 40nm CMOS process. It adopts error compensation processor (ECP) to improve the visual quality, and designs a memory management unit and resource sharing technique to improve the throughput and area efficiency by 38.5% and 34.3%, respectively. Moreover, a lossless compression processor (LCP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. The proposed TV SoC processor includes multi-standard 4K×2K@60fps playback and 3.4Gbps HDMI receiver (Rx), and both scenario dissipate 198.15mW at 1.2V core and 3.3V I/O.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"92 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 Symposium on VLSI Circuits Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2014.6858389","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A first-reported 4K×2K@60fps digital TV SoC processor supporting 9 video formats and integrating HDMI/MHL receiver is fabricated in a 40nm CMOS process. It adopts error compensation processor (ECP) to improve the visual quality, and designs a memory management unit and resource sharing technique to improve the throughput and area efficiency by 38.5% and 34.3%, respectively. Moreover, a lossless compression processor (LCP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. The proposed TV SoC processor includes multi-standard 4K×2K@60fps playback and 3.4Gbps HDMI receiver (Rx), and both scenario dissipate 198.15mW at 1.2V core and 3.3V I/O.
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