A Real-Time Fault-Tolerant and Power-Efficient Multicore System on Chip

Abstract

An approach to designing fault-tolerant and power-efficient multicore systems on chip for realtime information processing and control is proposed. It is assumed that a multicore system has a reserve on the chip, allowing for additional information processing. The approach is based on the rules of introducing redundancy aimed at reducing power consumption and the principles of system-level fault diagnosis, making it possible to decentralize the system recovery in case of failure.