Floating Body RAM Technology and its Scalability to 32nm Node and Beyond

T. Shino, Naoki Kusunoki, T. Higashi, Takashi Ohsawa, K. Fujita, K. Hatsuda, Nobuyuki Ikumi, Fumiyoshi Matsuoka, Yasuyuki Kajitani, Ryo Fukuda, Yoji Watanabe, Yoshihiro Minami, A. Sakamoto, Jun Nishimura, Hiroomi Nakajima, M. Morikado, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama
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引用次数: 35

Abstract

Technologies and improved performance of the floating body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the floating body cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant
浮动体RAM技术及其32nm及以上节点的可扩展性
展示了浮动体RAM的技术和改进性能。将SOI厚度降低到43nm,获得了16Mb的芯片良率68%。器件仿真证明,该浮体单元可扩展到32nm节点,保持信号裕度(阈值电压差)和数据保留时间不变
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