Jaesik Lee, J. Weiner, Hsin-Hung Chen, Y. Baeyens, V. Aksyuk, Young-Kai Chen
{"title":"CMOS-Based MEMS Mirror Driver for Maskless Lithography Systems","authors":"Jaesik Lee, J. Weiner, Hsin-Hung Chen, Y. Baeyens, V. Aksyuk, Young-Kai Chen","doi":"10.1109/CICC.2007.4405762","DOIUrl":null,"url":null,"abstract":"This paper presents a low-power MEMS mirror driver for maskless lithography systems. The CMOS driver consists of a 512 x 128 analog memory cell array to drive the position of 512 x 128 MEMS mirror array. The row driver employs an analog de-multiplexing architecture, which eliminates the need for precise matching among multiple row driver characteristics. It uses two parallel high-speed 8-b DACs with 128 sample-and-hold amplifiers (SHAs) to write a multilevel data into memory cells. To verify its functionality, a prototype test chip is implemented with a self-calibration technique to compensate the cell leakage. The driver chip is implemented in a 0.35-mum digital CMOS process. It consumes a 120 mA power with 3/3.6 V supplies.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2007.4405762","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a low-power MEMS mirror driver for maskless lithography systems. The CMOS driver consists of a 512 x 128 analog memory cell array to drive the position of 512 x 128 MEMS mirror array. The row driver employs an analog de-multiplexing architecture, which eliminates the need for precise matching among multiple row driver characteristics. It uses two parallel high-speed 8-b DACs with 128 sample-and-hold amplifiers (SHAs) to write a multilevel data into memory cells. To verify its functionality, a prototype test chip is implemented with a self-calibration technique to compensate the cell leakage. The driver chip is implemented in a 0.35-mum digital CMOS process. It consumes a 120 mA power with 3/3.6 V supplies.