A Cycle-Accurate Micro-Architecture Simulation Framework for Embedded Processors

Abstract

The growth in embedded systems applications and sophistication increased the need for rapid development and modeling of embedded processors. Embedded processors are usually application specific. This causes the strong need for modeling environments that can be used for rapid generation of detailed micro-architecture processor simulators. However, existing simulation tools in this category are far less mature and mostly commercial. This paper presents a generic cycle-accurate micro-architecture simulation framework for embedded processors. The framework is designed to generate an RTL (register transfer level) cycle accurate simulator. The framework is built in Java to provide features like extensibility, ability to be changed easily and platform independence. It provides the above features while being as fast as most known available frameworks. The paper uses ARM1022E as an example for embedded processors due to its wide range of applications like modems, cellular phones and automobiles. It simulates its two instruction set architectures (ISA): ARM (32-bit ISA) and THUMB (16-bit ISA). The paper verifies the framework by comparing the ARM simulator with ARMulator (from ARM Ltd.). It also compares the current simulation speed with available known frameworks. Lastly, the paper provides a study of ADPCM (adaptive differential pulse code modulation) decode performance on the ARM1022E processor using the framework