Efficient OS Hardware Accelerators Preemption Management in FPGA

Abstract

The management of reconfiguration in FPGAs constitutes a hot topic in a lot of domains. In such devices, a reconfigurable fabric is generally combined with a processor to guarantee high computing performance with a limited amount of hardware resources. Most of these devices generally feature an operating system (OS) that interacts with hardware Intellectual Property (IP) resources. Software tasks (managed by the OS) may then access hardware resources concurrently and dedicated mechanisms have to be provided to manage resource sharing efficiently. The problem is even bigger if hardware resources are localized in a reconfigurable area. In this paper, we deal with the problem of sharing hardware resources in a reconfigurable device. We propose a preemption mechanism for hardware resources that may reduce the reconfiguration time overhead to be compatible with the timing constraints of most embedded applications.