P. Paternoster, Andy Maki, A. Hernandez, Mark Grossman, M. Lau, David Sutherland, Aditya Mathad
{"title":"XBOX Series X: A Next-Generation Gaming Console SoC","authors":"P. Paternoster, Andy Maki, A. Hernandez, Mark Grossman, M. Lau, David Sutherland, Aditya Mathad","doi":"10.1109/ISSCC42613.2021.9366057","DOIUrl":null,"url":null,"abstract":"The XBOX Series X System-on-Chip (SoC) delivers an enormous improvement over the prior generation with up to $2 \\times$ GPU performance, $3 \\times$ CPU performance, $2.4 \\times$ GPU performance/W, $1.7 \\times$ memory bandwidth and $2 \\times$ IO bandwidth to feed the additional processing capability and features shown in Fig. 3.1.1. The chip is fabricated in TSMC’s N7 process node [6], containing 15.3B transistors on a 360.4mm2 die. It is packaged in $\\mathrm{a}52.5 \\times 52.5$ mm2 BGA using a 12-layer (5-2-5) substrate with 2963 balls and a 0.80mm minimum ball pitch. A die photo is shown in Fig. 3.1.7. The IO-limited chip floorplan is driven by DRAM connections on 3 sides of the chip.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC42613.2021.9366057","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The XBOX Series X System-on-Chip (SoC) delivers an enormous improvement over the prior generation with up to $2 \times$ GPU performance, $3 \times$ CPU performance, $2.4 \times$ GPU performance/W, $1.7 \times$ memory bandwidth and $2 \times$ IO bandwidth to feed the additional processing capability and features shown in Fig. 3.1.1. The chip is fabricated in TSMC’s N7 process node [6], containing 15.3B transistors on a 360.4mm2 die. It is packaged in $\mathrm{a}52.5 \times 52.5$ mm2 BGA using a 12-layer (5-2-5) substrate with 2963 balls and a 0.80mm minimum ball pitch. A die photo is shown in Fig. 3.1.7. The IO-limited chip floorplan is driven by DRAM connections on 3 sides of the chip.