A 3 GigaHertz 4:1 time division multiplexer with output retiming

Abstract

A 3 GHz 4:1 multiplexer has been designed in Hewlett Packard's newest bipolar process. The circuit is fully differential and uses ECL-level outputs. Inputs are also ECL levels. The design uses a travelling wave divider approach to generate the timing signals for a 4:1 series gated asynchronous multiplexer. An output flip-flop and an inverting (on-chip) delay line are used in conjunction to retime the output data. The chip operates to 3 GHz from approximately 100 MHz with a power dissipation of 1.8 W. Off-chip drivers are on chip terminated to approximately 100 Omega to present a VSWR of better than 2:1 at the output. Full input registers lock in the data at the inputs.<>