Keumsang Lim, HyangDuck Cho, Jaehwan Kim, Wooshik Kim
{"title":"A study on the implementation of the DSSS modem for a flight termination system","authors":"Keumsang Lim, HyangDuck Cho, Jaehwan Kim, Wooshik Kim","doi":"10.1109/ICACT.2005.245840","DOIUrl":null,"url":null,"abstract":"This paper describes the design of a direct sequence spread spectrum (DSSS) modem for a flight termination system using VHDL [R.K. Ducek, 2001] and FPGAs. The advantages of DSSS FTS includes the immunity from interference signals and anti-jamming effect. The error correcting scheme of a FTS uses (15,11) Reed-Solomon code. The spread codes of the inphase (I) and quadrature (Q) channel sequence can be generated using a gold sequence generator. The main algorithm is implemented in Altera APEX20K100E FPGAs","PeriodicalId":293442,"journal":{"name":"The 7th International Conference on Advanced Communication Technology, 2005, ICACT 2005.","volume":"68 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 7th International Conference on Advanced Communication Technology, 2005, ICACT 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICACT.2005.245840","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper describes the design of a direct sequence spread spectrum (DSSS) modem for a flight termination system using VHDL [R.K. Ducek, 2001] and FPGAs. The advantages of DSSS FTS includes the immunity from interference signals and anti-jamming effect. The error correcting scheme of a FTS uses (15,11) Reed-Solomon code. The spread codes of the inphase (I) and quadrature (Q) channel sequence can be generated using a gold sequence generator. The main algorithm is implemented in Altera APEX20K100E FPGAs