Efficient architectures for modulo 2n−1 squares

Abstract

Two novel architectures for designing modulo 2n−1 squarers are given. The first one does not perform any encoding on the input operand, while the second one uses Booth-encoding. Pre-layout estimates indicate that both architectures result in area and/or delay efficient modulo 2n−1 squarers. The non-encoded modulo squarers are more suitable for small values of n while the Booth-encoded modulo squarers are more suitable for medium and large values of n.