Fault-tolerant non-interference: invited talk abstract

David Sands
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Abstract

This work is about specifying and ensuring security in unreliable systems. We study systems which are subject to transient faults -- soft errors that cause stored values to be corrupted. Transient faults occur in hardware when a high-energy particle strikes a transistor, resulting in a spontaneous bit-flip. Such events have been acknowledged as the source of major crashes in server systems. The trend towards lower threshold voltages and tighter noise margins means that susceptibility to transient faults is increasing. From a security perspective, transient faults are a known attack vector. For instance, it has been shown that a single bit flip, regardless of how is triggered, can compromise the value of a secret key in some public key and authentication systems. Fault tolerance techniques aim to preserve properties of systems despite such transient faults. Preservation of functional correctness, however, comes at a high cost, and seems to inevitably require some special form of hardware-level replication. For the predominantly-software-based techniques, with one or two notable exceptions, most works do not give precise, formal guarantees. In this work, rather than attempting to preserve full functional behaviour in the presence of faults, we consider the novel problem of guaranteeing security: faults may cause a program to go wrong, but even if it goes wrong it should not leak sensitive data, no matter if the code is crafted with malicious intent. The particular security characterization we study is non-interference, an information-flow security property which says that public outputs of a program (the low security channel) do not reveal anything about its secrets (the high security inputs). Our approach has two distinguishing features. Firstly, it does not rely on special purpose fault tolerant hardware, and secondly, it makes its assumptions precise and provides formal guarantees. We study this problem for a RISC-style machine for which the only fault-tolerant component is the ROM containing the code, but otherwise contains no special fault-tolerant components. We devise a transformation technique for programs which generates fault-tolerant noninterfering code, up to a fixed number of faults. The method is based on a strong separation of resources between different security levels, inspired by the recent technique of Secure Multi-Execution, together with a carefully chosen code and data layout, and a robust protocol for data access and control flow modifications. We prove that the transformation method yields noninterfering programs in the presence of faults, and that it preserves the meaning of a class of reasonable programs -- those which use a bounded amount of storage and which are not sensitive to exactly where in memory code and data are located.
容错不干扰:特邀演讲摘要
这项工作是关于在不可靠的系统中指定和确保安全性。我们研究易发生瞬态故障的系统——导致存储值损坏的软错误。当高能粒子撞击晶体管时,硬件会发生瞬态故障,导致自发的位翻转。这类事件被认为是服务器系统中主要崩溃的根源。阈值电压越来越低,噪声边界越来越紧,这意味着对暂态故障的敏感性正在增加。从安全角度来看,瞬态故障是一种已知的攻击向量。例如,已经证明,单个比特翻转,无论如何触发,都可能危及某些公钥和身份验证系统中的秘密密钥的值。容错技术的目的是在这种瞬态故障下保持系统的特性。然而,保持功能正确性的代价很高,而且似乎不可避免地需要某种特殊形式的硬件级复制。对于主要基于软件的技术,除了一两个明显的例外,大多数作品都没有给出精确的、正式的保证。在这项工作中,我们不是试图在存在错误的情况下保留完整的功能行为,而是考虑保证安全性的新问题:错误可能导致程序出错,但即使它出错,也不应该泄露敏感数据,无论代码是否带有恶意。我们研究的特定安全特征是不干扰,这是一种信息流安全属性,它表示程序的公开输出(低安全通道)不会泄露任何有关其秘密(高安全输入)的信息。我们的方法有两个显著特点。首先,它不依赖于专用的容错硬件;其次,它使其假设精确并提供形式化保证。我们研究了一个risc风格的机器,其中唯一的容错组件是包含代码的ROM,但不包含特殊的容错组件。我们设计了一种程序转换技术,该技术可以在固定数量的错误下生成容错的无干扰代码。该方法基于不同安全级别之间的资源分离,受最新的安全多执行技术的启发,加上精心选择的代码和数据布局,以及用于数据访问和控制流修改的健壮协议。我们证明了这种转换方法在存在故障的情况下产生非干扰程序,并且它保留了一类合理程序的意义——这些程序使用有限的存储空间,并且对内存中代码和数据的确切位置不敏感。
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