Multi-objective optimization domino techniques for VLSI circuit

Abstract

The Domino logic circuits are often preferred in high performance designs because of the high speed and low area advantage it offers over CMOS static logic design. But in integrated circuits, the power consumed by clocking gradually takes a dominant part, and therefore research work in this paper is mainly focused on to study the comparative performance of various domino logic based techniques proposed in last decade and to evaluate the performance of the different domino techniques in terms of delay, power and their product (figure of merit) on BSIM4 model using Agilent Advanced Design System tool on 0.18μm CMOS process technology. The main focus of this work was to find the best Domino logic based technique that would provide best possible trade off to optimize multiple goals viz. area, power and speed at the same time to meet the multi-objective optimization goal for VLSI circuits.