Area tradeoffs in a 3D Programmable Structured ASIC

Abstract

A major obstacle to the uptake of advanced fabrication nodes by small industry is high NRE costs, mainly due to initial mask generation. The Programmable Structured ASIC (psASIC) is intended to bridge the gap between FPGA and Structured ASIC approaches to application design. The psASIC prototype environment comprises a pair of stacked chips, one containing only logic and the other comprising only interconnect and configuration RAM. Once an application has been prototyped and debugged, the interconnect layer can be replaced with a set of semi-standardized metallization masks in a way that preserves the critical timing paths of the prototype. We analyze the tradeoffs between vertical interconnect density and logic size in the psASIC using a 130nm 3D process as an example.