Standing Wave Oscillator Based Clock Distribution Minimizing Equivalent Capacitance for Process and Temperature variation

Abstract

The paper presents standing wave oscillator-based clock distribution minimizing equivalent capacitance (cd) for process and temperature variation. The SWOs have been proposed to enhance the negative resistance gd (an equivalent transconductance per ccp) to cancel the conductance in a transmission line. However, the SWOs have a parasitic capacitance which affects clock phase and unit length of the transmission line. In the proposed SWO, a MOS varactor, Cvar(V) (voltage-controlled capacitance), is added to minimize cd(equivalent capacitance per ccp). A phase locked loop and other peripherals are added to adjust the frequency and cdbecause the target frequency in the SWO varies due to process and temperature variation The design is simulated by a 180nm CMOS technology node with 1.8V power supply, and the total power consumption is 31.841 mW for the proposed architecture.