Compact DC model of a JVeSFET transistor with reduced number of empirical parameters

Abstract

VeSTIC (Vertical-Slit Transistor based Integrated Circuit) architecture enables easy integration of all types of transistors on the same chip. One of the elements available in this technology is Junction Vertical-Slit Field-Effect Transistor (JVeSFET). Simulation based feasibility studies indicate that the device exhibit attractive electrical properties like DC characteristics of relatively low subthreshold slope and may be considered as a good candidate for applications requiring low-noise and radiation-tolerant performance. A compact model of JVeSFET suitable for circuit simulators has been developed in this paper1. It includes a reduced number of empirical fitting parameters and is accurate and universal enough to provide for changes of the basic material parameter of the device.