CacheGuard: A Behavior Model Checker for Cache Timing Side-Channel Security: (Invited Paper)

Zi-Han Xu, Lingfeng Yin, Yongqiang Lyu, Haixia Wang, Gang Qu, Dongsheng Wang
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引用次数: 1

Abstract

Defending cache timing side-channels has become a major concern in modern secure processor designs. However, a formal method that can completely check if a given cache design can defend against timing side-channel attacks is still absent. This study presents CacheGuard, a behavior model checker for cache timing side-channel security. Compared to current state-of-the-art prose rule-based security analysis methods, CacheGuard covers the whole state space for a given cache design to discover unknown side-channel attacks. Checking results on standard cache and state-of-the-art secure cache designs discovers 5 new attack strategies, and potentially makes it possible to develop a timing side channel-safe cache with the aid of CacheGuard.
CacheGuard:缓存定时侧通道安全的行为模型检查器(特邀论文)
在现代安全处理器设计中,保护缓存定时侧信道已成为一个主要问题。然而,一种可以完全检查给定缓存设计是否可以防御定时侧信道攻击的正式方法仍然缺乏。本研究提出了CacheGuard,一种用于缓存定时侧信道安全的行为模型检查器。与当前最先进的基于规则的散文安全分析方法相比,CacheGuard覆盖了给定缓存设计的整个状态空间,以发现未知的侧信道攻击。在标准缓存和最先进的安全缓存设计上检查结果发现了5种新的攻击策略,并有可能在CacheGuard的帮助下开发一个定时侧通道安全缓存。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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