{"title":"A 3.75Gb/s CML output driver with configurable pre-emphasis in 65nm CMOS technology","authors":"Yong Fu, Zhiping Wen, Lei Chen","doi":"10.1145/3018009.3018048","DOIUrl":null,"url":null,"abstract":"This paper presents a configurable TX driver with 4-tap pre-emphasis to reduce the inter-symbol-interference (ISI) in high-speed transmission backplane, which is based on the FIR filter. The number of the tap, the selection of the main tap, the selection of the equalization approaches used in each tap and the coefficient of each tap all can be configured according to the particular channel conditions and the need of the receiver's equalizer, and the simulation result shows how the TX driver can reshape a signal based on the settings of the configurable ports. The design was implemented using 65nm CMOS technology. And HSPICE simulation results show that its line rates can be from 100 Mb/s to 3.75Gb/s.","PeriodicalId":189252,"journal":{"name":"Proceedings of the 2nd International Conference on Communication and Information Processing","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2nd International Conference on Communication and Information Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/3018009.3018048","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a configurable TX driver with 4-tap pre-emphasis to reduce the inter-symbol-interference (ISI) in high-speed transmission backplane, which is based on the FIR filter. The number of the tap, the selection of the main tap, the selection of the equalization approaches used in each tap and the coefficient of each tap all can be configured according to the particular channel conditions and the need of the receiver's equalizer, and the simulation result shows how the TX driver can reshape a signal based on the settings of the configurable ports. The design was implemented using 65nm CMOS technology. And HSPICE simulation results show that its line rates can be from 100 Mb/s to 3.75Gb/s.