Design Space Exploration for Scaled FeFET Nonvolatile Memories: High-k Spacer as a Powerful Aid

Abstract

This work explores the design space for scaled FeFET NVMs using TCAD simulations considering the phase non-uniformity of ferroelectric. Our study suggests that, to meet the requirements including the memory window (MW) and the electric field across interfacial layer (EIL), high-k spacers can be a powerful aid for future scaled FeFETs. High-k spacers improve EIL during write operation, mean MW and the worst MW under a nonuniform phase distribution. More importantly, these improvements increase with the down-scaling of gate length.