High speed pipeline ADC using dual-input op-amp to cancel memory effect

Abstract

A 100bit 200MS/s Pipeline ADC suing op-amp sharing and capacitor sharing architecture is proposed. In op-amp sharing pipeline ADC architecture, memory effect of residual charge occurs due to sharing an op-amp between two adjacent stages of the pipeline ADC. The proposed dual-input op-amp removes the memory effect in analog domain without complicated digital calibration. The dual-input op-amp simplifies the analog circuit, which reduces the die area. The ADC is implemented in TSMC 0.18μm 1P6M CMOS technology. The supply voltage is 1.8V. The simulation result shows 57.7dB SNDR and 61.13dB SFDR with a 98MHz input operating at a 200MS/s sampling rate. The area is 1.2mm × 1.2mm.