An Open-Loop Time Amplifier With Zero-Gain Delay in Output for Coarse-Fine Time to Digital Converters

Abstract

We present a new approach to an open-loop time amplifier. The proposed architecture achieves a time gain between 2 and 16 with zero-time duration to access the required gain. The input time difference range depending on the used gain varies from 6ns (for gain=2) to 781ps (for gain=16). We observed a measured maximum gain error of 3.75%. This structure is used in a 9-bit Time to Digital Converter (TDC) to obtain the digital output code. The design's parameter has been simulated in 0.18um CMOS technology. Corresponding to 9bits resolution, the simulation results show a minimum time resolution of 3.75ps and a maximum dynamic range of 1.92ns.