{"title":"An improved design of optical LIFO buffer with switched delay lines","authors":"Xiaoliang Wang, Xiaohong Jiang, A. Pattavina","doi":"10.1109/HPSR.2011.5986015","DOIUrl":null,"url":null,"abstract":"The lack of optical buffer is still one of the main problems that hinder the development of all optical networks. One approach to this problem is to emulate the behavior of optical buffers by using optical switches and fiber delay lines (SDL). Current works on this topic have demonstrated the feasibility of constructing SDL-based First In First Out (FIFO) buffer, Priority buffer, etc. The Last In First Out (LIFO) buffer is another important network component for congestion control and QoS guarantee, and parallel and cascade architectures have been peoposed for the efficient design of such optical buffer [1], [2]. The recent work in [3] showed that it is possible to use M fiber delay lines (FDLs) to construct a LIFO buffer of size B = (3/2) · 2M/2 − 1 and B = 2(M+1)/2 − 1 when M is even and odd, respectively. In this paper, we improve the work in [3] by providing a more efficient construction of SDL-based optical LIFO buffer. We first show that with a single stage feedback structure consisted of one (M + 1) × (M + 1) crossbar switch and M FDLs connecting M outputs of the crossbar back to M its inputs, we are able to construct a LIFO buffer of size B = 2 · 2M/2 − 2 and B = (3/2) · 2(M+1)/2 − 2 when M is even and odd, respectively. This is achieved through adopting a properly delay length setting for each FDL and a careful packets scheduling among FDLs, as well as exploiting the nice function of simultaneous packet reading and witting a FDL can support. We further show that if we adopt a cascade of smaller switches rather than a single (M+1)×(M+1) big switch, the new LIFO design can be implemented with much lower complexity in terms of the total number of basic 2 × 2 switch elements.","PeriodicalId":269137,"journal":{"name":"2011 IEEE 12th International Conference on High Performance Switching and Routing","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE 12th International Conference on High Performance Switching and Routing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HPSR.2011.5986015","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The lack of optical buffer is still one of the main problems that hinder the development of all optical networks. One approach to this problem is to emulate the behavior of optical buffers by using optical switches and fiber delay lines (SDL). Current works on this topic have demonstrated the feasibility of constructing SDL-based First In First Out (FIFO) buffer, Priority buffer, etc. The Last In First Out (LIFO) buffer is another important network component for congestion control and QoS guarantee, and parallel and cascade architectures have been peoposed for the efficient design of such optical buffer [1], [2]. The recent work in [3] showed that it is possible to use M fiber delay lines (FDLs) to construct a LIFO buffer of size B = (3/2) · 2M/2 − 1 and B = 2(M+1)/2 − 1 when M is even and odd, respectively. In this paper, we improve the work in [3] by providing a more efficient construction of SDL-based optical LIFO buffer. We first show that with a single stage feedback structure consisted of one (M + 1) × (M + 1) crossbar switch and M FDLs connecting M outputs of the crossbar back to M its inputs, we are able to construct a LIFO buffer of size B = 2 · 2M/2 − 2 and B = (3/2) · 2(M+1)/2 − 2 when M is even and odd, respectively. This is achieved through adopting a properly delay length setting for each FDL and a careful packets scheduling among FDLs, as well as exploiting the nice function of simultaneous packet reading and witting a FDL can support. We further show that if we adopt a cascade of smaller switches rather than a single (M+1)×(M+1) big switch, the new LIFO design can be implemented with much lower complexity in terms of the total number of basic 2 × 2 switch elements.