Architecture and implementation of a Restricted Boltzmann Machine for handwritten digits recognition

Abstract

Restricted Boltzmann Machines are artificial neural networks used in many types of statistical classification. In this work we present the architecture and implementation of such a neural network for fast recognition of hand-written digits. We use fixed and floating point arithmetic for minimizing the required hardware resources, and the use of pipeline results to a processing rate of more than 1 Mimages/sec per RBM. Four neural networks have been used on a PCIe-based hardware accelerator that uses a Virtex-7 FPGA, and that results to a total processing rate of more than 4 Mimages/sec.