A Software/Hardware Co-Design of Crystals-Dilithium Signature Scheme

Zhende Zhou, D. He, Zhe Liu, Min Luo, K. Choo
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引用次数: 18

Abstract

As quantum computers become more affordable and commonplace, existing security systems that are based on classical cryptographic primitives, such as RSA and Elliptic Curve Cryptography (ECC), will no longer be secure. Hence, there has been interest in designing post-quantum cryptographic (PQC) schemes, such as those based on lattice-based cryptography (LBC). The potential of LBC schemes is evidenced by the number of such schemes passing the selection of NIST PQC Standardization Process Round-3. One such scheme is the Crystals-Dilithium signature scheme, which is based on the hard module-lattice problem. However, there is no efficient implementation of the Crystals-Dilithium signature scheme. Hence, in this article, we present a compact hardware architecture containing elaborate modular multiplication units using the Karatsuba algorithm along with smart generators of address sequence and twiddle factors for NTT, which can complete polynomial addition/multiplication with the parameter setting of Dilithium in a short clock period. Also, we propose a fast software/hardware co-design implementation on Field Programmable Gate Array (FPGA) for the Dilithium scheme with a tradeoff between speed and resource utilization. Our co-design implementation outperforms a pure C implementation on a Nios-II processor of the platform Altera DE2-115, in the sense that our implementation is 11.2 and 7.4 times faster for signature and verification, respectively. In addition, we also achieve approximately 51% and 31% speed improvement for signature and verification, in comparison to the pure C implementation on processor ARM Cortex-A9 of ZYNQ-7020 platform.
晶体-锂离子签名方案的软硬件协同设计
随着量子计算机变得越来越便宜和普及,现有的基于经典密码原语(如RSA和椭圆曲线加密(ECC))的安全系统将不再安全。因此,人们对设计后量子加密(PQC)方案很感兴趣,例如基于格的加密(LBC)的方案。通过NIST PQC标准化过程第三轮选择的LBC方案的数量证明了LBC方案的潜力。其中一种方案是基于硬模-晶格问题的晶体-二锂签名方案。然而,晶体-二锂签名方案没有有效的实现。因此,在本文中,我们提出了一种紧凑的硬件架构,其中包含使用Karatsuba算法的精细模块化乘法单元以及NTT的地址序列和旋转因子的智能生成器,可以在短时钟周期内完成参数设置为diilithium的多项式加法/乘法。此外,我们在现场可编程门阵列(FPGA)上提出了一种快速的软件/硬件协同设计实现,用于Dilithium方案,在速度和资源利用率之间进行权衡。我们的协同设计实现在Altera DE2-115平台的Nios-II处理器上优于纯C实现,因为我们的实现在签名和验证方面分别快11.2倍和7.4倍。此外,与ZYNQ-7020平台的ARM Cortex-A9处理器上的纯C实现相比,我们还实现了大约51%和31%的签名和验证速度提升。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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