{"title":"Processing in Memory for Mathematics of Arrays Operations","authors":"I. Grout, L. Mullin","doi":"10.1109/ICPEI55293.2022.9986904","DOIUrl":null,"url":null,"abstract":"Processing In Memory (PIM), also referred to as Processor in Memory, is the integration of a processor with RAM (Random Access Memory) on a single Integrated Circuit (IC). In this paper, the concept of PIM is developed to support memory read/write requirements for Mathematics of Arrays (MoA) operations that implement tensor inner and outer products. The concept for MoA in PIM supports the integration of the processing operations and data storage memory, allowing for increases in processing speed and memory data transfer rate, and can support decreases in memory access latency and power usage.","PeriodicalId":223538,"journal":{"name":"2022 International Conference on Power, Energy and Innovations (ICPEI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 International Conference on Power, Energy and Innovations (ICPEI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICPEI55293.2022.9986904","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Processing In Memory (PIM), also referred to as Processor in Memory, is the integration of a processor with RAM (Random Access Memory) on a single Integrated Circuit (IC). In this paper, the concept of PIM is developed to support memory read/write requirements for Mathematics of Arrays (MoA) operations that implement tensor inner and outer products. The concept for MoA in PIM supports the integration of the processing operations and data storage memory, allowing for increases in processing speed and memory data transfer rate, and can support decreases in memory access latency and power usage.