Aleieldin Shamseldin, Hassan Soubra, Reham H. Elnabawy
{"title":"Performance of DSP operations implemented using a soft microprocessor: a case study based on Nios II","authors":"Aleieldin Shamseldin, Hassan Soubra, Reham H. Elnabawy","doi":"10.1109/ICM52667.2021.9664946","DOIUrl":null,"url":null,"abstract":"Digital Signal Processors are microprocessing units specially designed for performing operations on signals while optimizing performance. Soft-core processors are fully implemented using a hardware description language and are synthesized using the programmable logic resources available in a Field Programmable Gate Array.The objective addressed in this paper is measuring the ability of soft-core processors in performing digital signal processing algorithms. This paper presents the implementation of some signal processing operations in the Nios II soft-core Reduced Instruction Set Computer based processor. The performance of these operations is then evaluated by ensuring proper execution of functions and benchmarked against the TMS320DM64x+ DSP by Texas Instruments.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 International Conference on Microelectronics (ICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM52667.2021.9664946","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Digital Signal Processors are microprocessing units specially designed for performing operations on signals while optimizing performance. Soft-core processors are fully implemented using a hardware description language and are synthesized using the programmable logic resources available in a Field Programmable Gate Array.The objective addressed in this paper is measuring the ability of soft-core processors in performing digital signal processing algorithms. This paper presents the implementation of some signal processing operations in the Nios II soft-core Reduced Instruction Set Computer based processor. The performance of these operations is then evaluated by ensuring proper execution of functions and benchmarked against the TMS320DM64x+ DSP by Texas Instruments.